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FAN8060 -- 1.2MHz, 1A Synchronous Step-Down DC/DC Regulator
February 2009
FAN8060 1.2MHz, 1A Synchronous Step-Down DC/DC Regulator
Features
Current Mode Control Over 96% Efficient Selectable Continuous Output Current: 500mA/1A 2.5V to 5.5V Input Voltage Range Output Voltage as Low as 1.2V 1.2MHz Operating Frequency Less than 1A Shutdown Current External Synchronization from 500kHz to 2MHz 100% Duty Cycle Synchronous Switching FET; no Schottky Diode Required Stable with Ceramic Capacitors Light Load Mode with Pulse Skipping External Compensation External Soft-Start Overload / Short-Circuit Protection Under-Voltage Lockout Thermal Shutdown 10-Lead 3x3mm Green MLP Package
Description
The FAN8060 is a highly efficient, monolithic, currentmode, step-down synchronous regulator. It can provide 1A continuous current from 2.5V to 5.5V input voltage. The output voltage can be adjusted from 1.2V up to the input voltage with an external voltage divider. External compensation and soft-start allow for design optimization and flexibility. High-frequency operation allows for all-ceramic solutions and small footprints. In addition, a user-selectable current limit provides protection against output overload and short circuit. FAN8060 features pulse skipping to achieve higher efficiency during light load operation. 100% duty cycle capability enables power solutions to extend the drop out voltage. Provision for external synchronization allows users to minimize input capacitors and manage EMI in solutions. FAN8060 is available in a green, low profile, 10-Lead 3x3mm MLP package.
Applications
PDAs GPS Devices MP3 Players Mini PCI Digital Cameras Peripheral Ports DSP Core USB Devices PCMCIA Cable Modem Data Cards
Application Diagram
Figure 1. Typical Application Circuit
(c) 2008 Fairchild Semiconductor Corporation FAN8060 * Rev. 1.0.0 www.fairchildsemi.com
FAN8060 -- 1.2MHz, 1A Synchronous Step-Down DC/DC Regulator
Ordering Information
Part Number
FAN8060EMPX
Operating Temperature Range
-40 to +85C
Eco Status
Green
Package
10-Pin, 3x3mm Molded Leadless Package (MLP)
Packing Method
Tape & Reel
For Fairchild's definition of "green" Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html.
Pin Configuration
Figure 2. Pin Configuration (Top View) Note: 1. Connect exposed PAD to AGND
Pin Definitions
Pin
1 2 3 4 5 6 7 8 9 10
Name
EN AVIN PVIN SW PGND SYNC SS COMP FB AGND
Function
Enable. Enables operation when pulled to logic HIGH. Analog Input Voltage. All internal control circuits are connected to this supply. Power Input Voltage. Power stage supply voltage. Switching Node. The drains of both PMOS and NMOS. Power Ground. Power return and source of the power NMOS Synchronization. Use this pin to synchronize the part to an external clock. This pin also controls current limit threshold. Tie to ground for 1.0A or tie to VIN for 0.5A continuous load current. When an external clock is applied, the default current setting is 1A. This pin has a pull-down resistor of 450K. Soft-Start. A capacitor connected between this pin and AGND can set soft-start time. Compensation. Error amplifier output. Connect the external compensation network between this pin and AGND. Output Voltage Feedback. Connect through a resistor divider to set the output voltage. Analog Ground. Ground return for all internal control circuits.
(c) 2008 Fairchild Semiconductor Corporation FAN8060 * Rev. 1.0.0
www.fairchildsemi.com 2
FAN8060 -- 1.2MHz, 1A Synchronous Step-Down DC/DC Regulator
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. All voltage values, except differential voltages, are given with respect to the network ground terminal. Stress beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
Symbols
VPVIN VAVIN VSW TSTG TJ ESD PVIN (AGND=PGND) AVIN (AGND=PGND)
Parameter
Min.
-0.3 -0.3 -0.3 -0.3 -65 -40
Max.
6.0 6.0 VIN + 0.3 or 6.0 6.0 +150 +125
Unit
V V V V C C kV
Switch Voltage, SW to GND All other pins except COMP Storage Temperature Junction Temperature Electrostatic Discharge Protection Human Body Model, JESD22-A114 Charged Device Model, JESD22-C101
2.0 2.5
Note: 2. COMP pin has an internal clamp to 1.5V.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
VIN TA Supply Voltage
Parameter
Ambient Operating Temperature
Min.
2.5 -40
Max.
5.5 +85
Unit
V C
Thermal Information
Symbol
TSTG TL JA Jc PD Storage Temperature Lead Soldering Temperature, 30 Seconds Thermal Resistance: Junction-to-Ambient Thermal Resistance: Junction-to-Case
(3) (3)
Parameter
Min.
-65
Typ.
Max.
+150 +300
Units
C C C/W C/W
49 8 1.3
Total Power Dissipation in the package, TA=25C
W
Note: 3. Typical thermal resistance when mounted on a four-layer PCB. Actual results are dependent upon mounting method and surface related to the design.
(c) 2008 Fairchild Semiconductor Corporation FAN8060 * Rev. 1.0.0
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FAN8060 -- 1.2MHz, 1A Synchronous Step-Down DC/DC Regulator
Electrical Characteristics
VIN=5.0V, VOUT=2.5 V, COUT=10F, CIN=10F, over operating range, unless otherwise noted.
Symbol
Basic Operation VIN IQ ISD VUVLO VUVLOHYS VENH VENL RONPMOS
Parameter
VIN Operating Voltage Quiescent Current Shutdown Current VIN Under-Voltage Lockout VIN Under-Voltage Lockout Hysteresis Enable High Input Voltage Enable Low Input Voltage PMOS On Resistance
(4)
Conditions
AVIN=PVIN VEN=5 V, VSS=0V VEN=0V Rising VIN
Min.
2.5 250
Typ.
Max.
5.5
Units
V A A V mV
371 0.34
500 0.60 2.25
2.10
2.19 70 1.70
2.00
V V m
0.80 VIN=5V VIN=3.3V
1.22 200 300 200 300 1.2 0.6
RONNMOS
NMOS On Resistance
(4)
VIN=5V VIN=3.3V VSYNC=0V VSYNC=VIN TA=25C Rising Edge VSYNC=Square Wave VSYNC On Time Sink/Source Current 30 700
(4) GEA (4) AVEA
m
ILIM fOSC VSYNC fSYNC tSYNC
P-Channel Current Limit VFB=0.7V, VIN=5V, 100% Duty Cycle Oscillator Frequency SYNC Threshold Synchronization Frequency Minimum SYNC Pulse Width
A 1.35 MHz V 2000 KHz ns 60 1400 A A/V V/V A/V 1.229 0 -4.3 V A A
1.105
1.21 VIN/2
500 100 45 1000 550 3
IAMP
Error Amplifier
(4)
GCS VREF IFB ISS
Current Sense Gain
Reference Voltage for Temperature Co-efficient, see Figure 12 FB Bias Current Soft-Start Current
(4)
Measured at FB Pin TA=25C TA=25C
1.181 -0.10 -4.8
1.205 -0.06 -4.5
Protections TOTP THYS Over-Temperature Threshold +165 +20 C C
Over-Temperature Hysteresis
Note: 4. Guaranteed by design and characterization; not production tested.
(c) 2008 Fairchild Semiconductor Corporation FAN8060 * Rev. 1.0.0
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FAN8060 -- 1.2MHz, 1A Synchronous Step-Down DC/DC Regulator
Functional Block Diagram
AVIN SYNC
To Internal Supply
PVIN +
Current Sense
450k
-
+ + Slope Compensation
Oscillator
EN Enable & Reference
OTP
4uA
Log ic & Driver
SW
PWM
Vref
SS
+ + + + -GM
1.4V
+ -
Pulse Skip + -
FB
PGND
Short Circuit Protection COMP
Low Current Detect
AGND
Figure 3. Functional Block Diagram
(c) 2008 Fairchild Semiconductor Corporation FAN8060 * Rev. 1.0.0
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FAN8060 -- 1.2MHz, 1A Synchronous Step-Down DC/DC Regulator
Operation Description
The FAN8060 is a step-down converter operating in current-mode PWM architecture with a typical switching frequency of 1.2MHz. At the beginning of each clock cycle, the P-channel transistor is turned on. The current in the inductor ramps up and is sensed via an internal circuit. The P-channel switch is turned off when the sensed current causes the PWM comparator to trip, which is when the output voltage is in regulation or when the inductor current reaches the current limit (set internally to 1.2A, typically). After a minimum dead time to prevent shoot-through current, the N-channel transistor is turned on and the current ramps down. As the clock cycle is completed, the N-channel switch is turned off and the next clock cycle starts.
Soft Start
When the input voltage on AVIN exceeds the UVLO threshold and EN is high, the circuit releases SS and enables the PWM regulator. A capacitor connected to the SS pin and AGND is charged by a 4A internal current source, causing the voltage on the capacitor to rise. When this voltage reaches 1.2V, the output is in regulation. The SS voltage continues to rise to AVIN. The time for the output to reach regulation is given by the following equation:
t (ms ) =
(4A / 1.2V )
CSS (nF )
(1)
Light Load Operation
As the output load reduces, the current in the inductor during off time is sensed across the low side MOSFET. When the current reverses direction, the low-side MOSFET is turned off and the high-side MOSFET is not turned on until the output is out of regulation.
Output overload and short-circuit protection is active during soft-start. When the part is disabled, SS pin is pulled low internally.
Overload & Short-Circuit Protection
FAN8060 employs cycle-by-cycle current limiting, which limits current by reducing duty cycle during overload. As the load increases beyond the limit, the output voltage starts to reduce, thereby reducing the FB voltage. When the FB node is half the reference voltage and the COMP node has reached maximum value, short-circuit protection is detected. At that time, both the SS pin and the COMP pin are pulled to ground until the inductor current crosses zero. At that point, both SS and COMP are released for the current to ramp up again. This continues until the short-circuit condition is released.
100% Duty Cycle Operation
As the input voltage approaches the output voltage, the controller starts to increase the duty cycle to maintain output regulation until duty cycle reaches 85%. The controller then transitions to a 100% duty cycle mode over several cycles to support the load. When the dropout condition is met, the converter turns the Pchannel high side continuously on. In this mode, the output voltage is equal to the input voltage, minus the voltage drop across the P-channel MOSFET.
(c) 2008 Fairchild Semiconductor Corporation FAN8060 * Rev. 1.0.0
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FAN8060 -- 1.2MHz, 1A Synchronous Step-Down DC/DC Regulator
Typical Performance Characteristics
VIN=5V, VOUT=2.4V, L=3.3H, CIN=10F, COUT=10F, fS=1.2MHz, TA=25C, unless otherwise noted.
EN(2V/div.) VSW (2V/div.) EN(2V/div.) VSW (2V/div.) VOUT(2V/div.) IL((1A/div.) [1ms/div.] Figure 4. EN Startup with 1A Load VOUT(2V/div.) IL((1A/div.) [1ms/div.] Figure 5. EN Turn off with 1A Load
VSW (2V/div.)
VSW (2V/div.)
VOUT(2V/div.)
VOUT(2V/div.)
IL((1A/div.) [500ns/div.] Figure 6. PWM Operation with 1A Load
IL((1A/div.) [200ns/div.] Figure 7. 2MHz Sync Operation with 1A Load
VOUT(10mV/div. AC coupled) VOUT(50mV/div. AC coupled) VSW (2V/div.)
IOUT(500mA/div.)
Slew rate : 2.5A/us
IL((1A/div.) [200s/div.] Figure 8. Load Transient Response(Step-up/down) [500ns/div.] Figure 9. Output Voltage Ripple with 1A Load
(c) 2008 Fairchild Semiconductor Corporation FAN8060 * Rev. 1.0.0
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FAN8060 -- 1.2MHz, 1A Synchronous Step-Down DC/DC Regulator
Typical Performance Characteristics (Continued)
VIN=5V, VOUT=2.4V, L=3.3H, CIN=10F, COUT=10F, fS=1.2MHz, TA=25C, unless otherwise noted.
0.10 0.05 0.00 -0.05
VOUT [%]
98
3.3VIN/2.4VO
3.3VIN/2.4VO
Efficiency [%]
95 92 89 86 83 80
-0.10 -0.15 -0.20 -0.25 -0.30 0 0.2 0.4 0.6 0.8 1
Load Current [A]
5VIN/2.4VO
5VIN/2.4VO
0
0.2
0.4
0.6
0.8
1
Load Current [A]
Figure 10. Normalized VOUT vs. Load Current
4.00
Figure 11. Efficiency vs. Load Current
2.00
Frequency [%]
VREF [%]
0.00
-2.00
-4.00 -50 -25 0 25 50 75 100
Temperature []
Temperature []
Figure 12. Normalized VREF vs. Temperature
Figure 13. Normalized Oscillation Frequency vs. Temperature
(c) 2008 Fairchild Semiconductor Corporation FAN8060 * Rev. 1.0.0
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FAN8060 -- 1.2MHz, 1A Synchronous Step-Down DC/DC Regulator
Applications Information
Refer to Figure 1 for reference designators.
Input Capacitor Selection
The input capacitor reduces the RMS current drawn from the input and switching noise from the device. The combined RMS current rating for the input capacitor should be greater than the value calculated by the following equation:
I RMS = IOUTMAX ( D - D 2 )
Output Voltage Setting
The output voltage of the FAN8060 can be set from 1.2V to VIN by an external resistor divider, given by the following equation:
VOUT = 1.2(1 + R2 ) R3
(2)
(5)
where, VOUT equals the output voltage.
where: IRMS = RMS current of the input capacitor; and IOUTMAX = Maximum output current. Small, high value, inexpensive, lower-ESR ceramic capacitors are recommended; 10F ceramic capacitors with X7R or X5R should be adequate for 1A applications.
Inductor Selection
Typically, the inductor value is chosen based on ripple current (IL), which is chosen between 10% and 35% of the maximum DC load. Regulator designs that require fast transient response use a higher ripple-current setting, while regulator designs that require higher efficiency keep ripple current on the low side and operate at a lower switching frequency. For a given output voltage ripple requirement, L can be calculated by the following equation:
L VOUT (1 - D ) I L fS
Loop Compensation
The loop is compensated using a feedback network connected between COMP and AGND. Figure 14 shows a Type-2 compensation network used to stabilize the FAN8060.
Vout
(3)
where; D fS = = Duty ratio (VO/VIN); Switching frequency; and
R2 VFB R3
Gm
Ve RC CA CC
IL = Inductor ripple value, typically set to 10% 35% of the maximum steady-state load current. The inductor should have a low DCR to minimize the conduction losses and maximize efficiency. Some recommended inductors are suggested in Table 1: Table 1. Recommended Inductors (3.3H) Size[mm2] 7x7x3 5x5x2 4x4x2 2.6x2.8x1.2 DCR 23m 60m 78m 130m Part Number SLF7032T-3R3 LTF5022T-3R3 VLCF4020T-3R3 VLF3012AT-3R3 Vendor TDK TDK TDK TDK
Vref
+
Figure 14. Compensation Network The goal of the compensation design is to shape the frequency response of the converter to achieve high DC gain and fast transient, while maintaining loop stability. FAN8060 employs peak-current-mode control for easy use and fast transient response. Current mode control helps simplify the loop to a one-pole and one zero system. The DC gain of the voltage feedback loop is given by:
AVDC = RL GCS AVEA VFB VOUT
Output Capacitor Selection
The output capacitor is selected based on the needs of the final application and its output ripple requirements. A larger output capacitor value reduces the output ripple voltage. The formula of output ripple VOUT is:
1 VOUT IL ESR + 8 COUT fS
(6)
where: AVDC = DC gain of the feedback loop; RL = Load resistor value (VOUT/IOUT); GCS = Current sense gain (3A/V); AVEA = Error amplifier voltage gain (550V/V); and VFB = Feedback threshold voltage (1.2V).
(4)
where COUT is the output capacitor. ESR is the equivalent series resistance of the output capacitor.
(c) 2008 Fairchild Semiconductor Corporation FAN8060 * Rev. 1.0.0
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FAN8060 -- 1.2MHz, 1A Synchronous Step-Down DC/DC Regulator
The system pole is calculated by the equation:
fP 1 = 1 2 COUT RL
(7)
If required, add the second compensation capacitor (CA) to set the pole fP3 at the location of the ESR zero. Determine (CA) value by the equation:
CA = COUT ESR RC
The system zero is due to the output capacitor and its ESR. System zero is calculated by the equation:
f z1 = 1 2 COUT ESR
(14)
(8)
The output characteristics of the error (Gm) amplifier are controlled by a series capacitor and resistor network connected at the COMP pin to GND. The pole is calculated by the following equation:
f p2 GEA = 2 CC AVEA
Design Example
Table 2 provides component values for delivering various output voltages with loads up to 1A with VIN at 5V (+/-10% tolerance). Table 2. Recommended Feedback and Compensation Values (VIN=5V) VO
1.2V 1.5V 1.8V 10F 3.3H 2.5V 3.3V
(9)
C4
L1
R2
Short
R3
Open
R1
C5
C2
where: GEA = Error Amplifier Transconductance (1000A/V); and CC = compensation capacitor. Zero is due to the compensation capacitor (CC) and resistor (RC) calculated by the following equation:
fz 2 = 1 2 CC RC
2.55k 10.2k 5.9k 16.2k 11.8k 4.7k 1.5nF 150pF 15k
18.7k 10.7k
(10)
where RC is compensation resistor. The system crossover frequency (fC), where the control th loop has unity gain, is recommended to be set at 1/10 of switching frequency. Generally, higher fC means faster response to load transients, but can result in instability if not properly compensated. The first step in compensation design is choosing the compensation resistor (RC) to set the crossover frequency by the following equation:
RC = 2 COUT fC VOUT GCS GEA VFB
Figure 15. Recommended Schematic (5VIN to 2.5VO)
(11)
where VFB is reference voltage. The next step is choosing the compensation capacitor (CC) to achieve the desired phase margin. For applications with typical inductor values, setting the compensation zero, fZ2, to below one fourth of the crossover frequency provides sufficient phase margin. Determine the (CC) value by the following equation:
CC = 2
RC fC
(12)
Then determine if the second compensation capacitor (CA) is required. It is required if the ESR zero of the output capacitor is located at less than half of the switching frequency.
f 1 (13)
(c) 2008 Fairchild Semiconductor Corporation FAN8060 * Rev. 1.0.0
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FAN8060 -- 1.2MHz, 1A Synchronous Step-Down DC/DC Regulator
PCB Layout Recommendations
The switching power supply PCB layout needs careful attention and is critical to achieving low losses and clean and stable operation. Although each design is different, below are some general recommendations for a good PCB layout. Keep the high-current traces and load connectors as short and wide as possible. These traces consist of VIN, GND, VOUT, and SW. Place the input capacitor, the inductor, and the output capacitor as close as possible to the IC terminals. Keep the loop area between SW node, inductor, and output capacitors as small as possible; minimizing ground loops to reduce EMI issues. Route high-dV/dt signals, such as SW node, away from the error amplifier input/output pins. Keep components connected to the FB and COMP pins close to the pins. Figure 16. Recommended PCB Layout
(c) 2008 Fairchild Semiconductor Corporation FAN8060 * Rev. 1.0.0
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FAN8060 -- 1.2MHz, 1A Synchronous Step-Down DC/DC Regulator
Physical Dimensions
0.15 C 3.0 A B
0.78 0.55
10
2X
2.25 2.20 2.00
6
2.33
3.0
0.15 C
0.23 0.02 D 1 0.50 5 0.25
0.8 MAX
0.10 C
TOP VIEW
2X
RECOMMENDED LAND PATTERN
(0.20)
0.08 C
0.05 0.00
SEATING PLANE
SIDE VIEW
(3.000.10) 2.250.05 (0.38) 1 5
C
PIN #1 IDENT
1.550.05
(3.000.10)
0.400.05 0.5 10 2.0
0.30 0.20
6 0.10 0.05 CAB C
BOTTOM VIEW
A. CONFORMS TO JEDEC REGISTRATION MO-229, VARIATION WEED-5 B. DIMENSIONS ARE IN MILLIMETERS. C. DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994 D. LAND PATTERN DIMENSIONS ARE NOMINAL REFERENCE VALUES ONLY MLP10BrevA
Figure 17. 10-Pin, 3x3mm Molded Leadless Package (MLP)
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild's worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor's online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/.
(c) 2008 Fairchild Semiconductor Corporation FAN8060 * Rev. 1.0.0
1.55 2.00 3.10
www.fairchildsemi.com 12
FAN8060 -- 1.2MHz, 1A Synchronous Step-Down DC/DC Regulator
(c) 2008 Fairchild Semiconductor Corporation FAN8060 * Rev. 1.0.0
www.fairchildsemi.com 13

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